IEEE - Institute of Electrical and Electronics Engineers, Inc. - Thru-silicon vias for 3D WLP

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces

Author(s): Savastionk, S. ; Siniaguine, O. ; Korczynski, E.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2000
Conference Location: Braselton, GA, USA
Conference Date: 8 August 2000
Page(s): 206 - 207
ISBN (Paper): 0-930815-59-9
DOI: 10.1109/ISAPM.2000.869271
Regular:

Thru-Silicon designs and manufacturing process flows are introduced as a means to produce 3D wafer level packaging solutions. Standard silicon IC manufacturing unit-processes must be combined into... View More

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