IEEE - Institute of Electrical and Electronics Engineers, Inc. - Wafer level package using double balls

Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces

Author(s): Topper, M. ; Glaw, V. ; Coskina, P. ; Auersperg, J. ; Samulewicz, K. ; Lange, M. ; Karduck, C. ; Fehlberg, S. ; Ehrmann, O. ; Reichl, H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2000
Conference Location: Braselton, GA, USA
Conference Date: 8 August 2000
Page(s): 198 - 200
ISBN (Paper): 0-930815-59-9
DOI: 10.1109/ISAPM.2000.869269
Regular:

The highest potential for future single chip packages has the wafer level approach: the package is completed directly on the wafer, then singulated by dicing for assembly in a flip chip fashion.... View More

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