IEEE - Institute of Electrical and Electronics Engineers, Inc. - A fully associative software-managed cache design

Proceedings of 27th International Symposium on Computer Architecture

Author(s): E.G. Hallnor ; S.K. Reinhardt
Sponsor(s): IEEE Comput. Soc. Tech. Committee on Comput. Archit.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2000
Conference Location: Vancouver, BC, Canada, Canada
Conference Date: 14 June 2000
Page Count: 10
Page(s): 107 - 116
ISBN (Paper): 1-58113-232-8
ISSN (Paper): 1063-6897
DOI: 10.1145/339647.339660
Regular:

As DRAM access latencies approach a thousand instruction-execution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue to be... View More

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