IEEE - Institute of Electrical and Electronics Engineers, Inc. - An optimized integration scheme for 0.13 /spl mu/m technology node dual-damascene Cu interconnect

Proceedings of the IEEE 2000 International Interconnect Technology Conference

Author(s): Shyue-Shyh Lin ; Chih-Wei Chen ; Shien-Ming Huang ; Tsung-Kuei Kang ; Chen-Nan Yeh ; Tsyr-Lih Li ; Bing-Yue Tsui ; Hsia, C.C.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2000
Conference Location: Burlingame, CA, USA
Conference Date: 7 June 2000
Page(s): 273 - 275
ISBN (Paper): 0-7803-6327-2
DOI: 10.1109/IITC.2000.854346
Regular:

From electrical simulations, the best performance dual damascene Cu/FSG integration scheme has been defined to be via first without etching stop layer and with thinnest possible sealing nitride... View More

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