IEEE - Institute of Electrical and Electronics Engineers, Inc. - Quantitative analysis on Cu diffusion through TaN barrier metal and the device degradation by using two-level Cu-interconnects implemented 0.25 /spl mu/m-256 Mbit DRAMs

Proceedings of the IEEE 2000 International Interconnect Technology Conference

Author(s): Kawanoue, T. ; Iijima, T. ; Matsuda, T. ; Yamada, Y. ; Morikado, M. ; Sugimae, K. ; Kajiyama, T. ; Maekawa, H. ; Hamamoto, T. ; Kumagai, J. ; Kaneko, H. ; Hayasaka, N.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2000
Conference Location: Burlingame, CA, USA
Conference Date: 7 June 2000
Page(s): 199 - 201
ISBN (Paper): 0-7803-6327-2
DOI: 10.1109/IITC.2000.854324
Regular:

To evaluate Cu diffusion in a practically used damascene structure, plasma-enhanced CVD-SiO/sub 2/ (p-SiO/sub 2/) layer with trench test structure was used, and trace Cu diffusion into the... View More

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