IEEE - Institute of Electrical and Electronics Engineers, Inc. - Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging

2000 Proceedings. 50th Electronic Components and Technology Conference

Author(s): Topper, M. ; Auersperg, J. ; Glaw, V. ; Kaskoun, K. ; Prack, E. ; Keser, B. ; Coskina, P. ; Jager, D. ; Fetter, D. ; Ehrmann, O. ; Samulewicz, K. ; Meinherz, C. ; Fehlberg, S. ; Karduck, C. ; Reichl, H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2000
Conference Location: Las Vegas, NV, USA, USA
Conference Date: 21 May 2000
Page(s): 74 - 80
ISBN (Paper): 0-7803-5908-9
DOI: 10.1109/ECTC.2000.853121
Regular:

Wafer Level Packaging has the highest potential for future single chip packages. The package is completed directly on the wafer then singulated by dicing for the assembly in a flip chip fashion.... View More

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