IEEE - Institute of Electrical and Electronics Engineers, Inc. - Masking and etching of silicon and related materials for geometries down to 25 nm

IECON'99. Conference Proceedings. 25th Annual Conference of the IEEE Industrial Electronics Society

Author(s): Hilleringmann, U. ; Vieregge, T. ; Horstmann, J.T.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Jose, CA, USA, USA
Conference Date: 29 November 1999
Volume: 1
ISBN (Paper): 0-7803-5735-3
DOI: 10.1109/IECON.1999.822171
Regular:

This paper describes a technique to generate structures down to 25 nm in width on top of a silicon wafer, applying layer deposition and anisotropic dry etching processes. Due to the excellent... View More

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