IEEE - Institute of Electrical and Electronics Engineers, Inc. - Fault secure binary counter design

ICECS'99. Proceedings of ICECS'99. 6th IEEE International Conference on Electronics, Circuits and Systems

Author(s): Karaolis, E. ; Nikolaidis, S. ; Goutis, C.E.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Pafos, Cyprus, Cyprus
Conference Date: 5 September 1999
Volume: 3
ISBN (Paper): 0-7803-5682-9
DOI: 10.1109/ICECS.1999.814493
Regular:

An architecture for fault secure synchronous binary counters is introduced in this paper. It is based on the parity prediction technique. At each counter state the parity of the counter outputs of... View More

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