IEEE - Institute of Electrical and Electronics Engineers, Inc. - Verification of scheduling in the presence of loops using uninterpreted symbolic simulation

Proceedings. 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD'99

Author(s): Ashar, P. ; Raghunathan, A. ; Gupta, A. ; Bhattacharya, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Austin, TX, USA, USA
Conference Date: 10 October 1999
Page(s): 458 - 466
ISBN (Paper): 0-7695-0406-X
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.1999.808581
Regular:

We propose a novel procedure based on uninterpreted symbolic simulation for checking the scheduling step in high-level synthesis. The primary task in scheduling is the assignment of time steps or,... View More

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