IEEE - Institute of Electrical and Electronics Engineers, Inc. - Fault simulation based test generation for combinational circuits using dynamically selected subcircuits

Proceedings. 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD'99

Author(s): Pomeranz, I. ; Reddy, S.M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Austin, TX, USA, USA
Conference Date: 10 October 1999
Page(s): 412 - 417
ISBN (Paper): 0-7695-0406-X
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.1999.808575
Regular:

We propose a fault simulation based method to generate test patterns that achieve high fault coverages for combinational circuits. Due to the use of fault simulation, the proposed method is... View More

Advertisement