IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design for testability to combat delay faults

Proceedings. 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD'99

Author(s): Savir, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Austin, TX, USA, USA
Conference Date: 10 October 1999
Page(s): 407 - 411
ISBN (Paper): 0-7695-0406-X
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.1999.808574
Regular:

To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. The paper describes a new... View More

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