IEEE - Institute of Electrical and Electronics Engineers, Inc. - Multi-level logic minimization through fault dictionary analysis

Proceedings. 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD'99

Author(s): Mehler, R.W. ; Mercer, M.R.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Austin, TX, USA, USA
Conference Date: 10 October 1999
Page(s): 315 - 318
ISBN (Paper): 0-7695-0406-X
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.1999.808558
Regular:

Presents the results of the study of a new algorithm for multi-level logic minimization. The study is based on the premise that an untestable node is a redundant node, and that nodes that do not... View More

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