IEEE - Institute of Electrical and Electronics Engineers, Inc. - Yield optimization by design centering and worst-case distance analysis

Proceedings. 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD'99

Author(s): Samudra, G.S. ; Chen, H.M. ; Chan, D.S.H. ; Ibrahim, Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Austin, TX, USA, USA
Conference Date: 10 October 1999
Page(s): 289 - 290
ISBN (Paper): 0-7695-0406-X
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.1999.808550
Regular:

Process variations invariably give rise to a parametric yield below 100% for VLSI circuits. Improving the yield by choosing a set of optimum parameter values does not incur any extra cost, and it... View More

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