IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design and implementation of a parallel weighted random pattern and logic built in self test algorithm

Proceedings. 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD'99

Author(s): Chang, P. ; Keller, B. ; Paliwal, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Austin, TX, USA, USA
Conference Date: 10 October 1999
Page(s): 175 - 180
ISBN (Paper): 0-7695-0406-X
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.1999.808423
Regular:

An increase in chip densities has led to a significant increase in test generation and fault simulation times. Analysis of various test methodologies has shown that logic built in self test... View More

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