IEEE - Institute of Electrical and Electronics Engineers, Inc. - Task-level partitioning and RTL design space exploration for multi-FPGA architectures

Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Author(s): Srinivasan, V. ; Vemuri, R.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Napa Valley, CA, USA, USA
Conference Date: 23 April 1999
Page(s): 272 - 273
ISBN (Paper): 0-7695-0375-6
DOI: 10.1109/FPGA.1999.803694
Regular:

This paper presents SPADE, a system for partitioning designs onto multi-FPGA architectures. The input to SPADE is a task graph, that is composed of computational tasks, memory tasks and the... View More

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