IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 60 nm channel length silicon stacked tunnel transistor

1999 57th Annual Device Research Conference Digest

Author(s): K. Itoh ; H. Mizuta ; H. Ahmed
Sponsor(s): IEEE Electron Devices Soc
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Santa Barbara, CA, USA, USA
Conference Date: 23 June 1999
Page Count: 2
Page(s): 132 - 133
ISBN (Paper): 0-7803-5170-3
DOI: 10.1109/DRC.1999.806346
Regular:

The transistor is a vertical, fully depleted double-gate SOI-MOSFET (silicon-on-insulator metal-oxide-semiconductor-field-effect-transistor) with barriers in the channel... View More

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