IEEE - Institute of Electrical and Electronics Engineers, Inc. - Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study

European Test Workshop 1999

Author(s): Renovell, M. ; Portal, J.M. ; Figueras, J. ; Zorian, Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Constance, Germany, Germany
Conference Date: 25 May 1999
Page(s): 146 - 151
ISBN (Paper): 0-7695-0390-X
DOI: 10.1109/ETW.1999.804520
Regular:

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach concerns the XILINX4000 family. On this... View More

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