IEEE - Institute of Electrical and Electronics Engineers, Inc. - Circuit styles and strategies for CMOS VLSI design on SOI

Proceedings. 1999 International Symposium on Low Power Electronics and Design

Author(s): F. Assaderaghi
Sponsor(s): ACM/SIGDA
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Diego, CA, USA, USA
Conference Date: 17 August 1999
Page Count: 6
Page(s): 282 - 287
ISBN (Paper): 1-58113-133-X
DOI: 10.1145/313817.313955
Regular:

This paper reviews specific circuit styles and strategies employed in the design of CMOS VLSI on partially-depleted (PD) SOI. These strategies address issues and problems that arise on PD SOI... View More

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