IEEE - Institute of Electrical and Electronics Engineers, Inc. - An optimization technique for dual-output domino logic

Proceedings. 1999 International Symposium on Low Power Electronics and Design

Author(s): S. Ramprasad ; I.N. Hajj ; F.N. Najm
Sponsor(s): ACM/SIGDA
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Diego, CA, USA, USA
Conference Date: 17 August 1999
Page Count: 3
Page(s): 258 - 260
ISBN (Paper): 1-58113-133-X
DOI: 10.1145/313817.313939
Regular:

Dynamic logic circuits are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. One well-known dynamic logic family is the domino CMOS family, which,... View More

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