IEEE - Institute of Electrical and Electronics Engineers, Inc. - Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

1999 Symposium on VLSI Circuits. Digest of Technical Papers

Author(s): T. Namekawa ; S. Miyano ; R. Fukuda ; R. Haga ; O. Wada ; H. Banba ; S. Takeda ; K. Suda ; K. Mimoto ; S. Yamaguchi ; T. Ohkubo ; H. Takato ; K. Numata
Sponsor(s): Japan Soc. Appl. Phys.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 17 June 1999
Page Count: 4
Page(s): 149 - 152
ISBN (Paper): 4-930813-95-6
DOI: 10.1109/VLSIC.1999.797267
Regular:

A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is proposed. This redundancy saves an area of spare cells from 6% to 1.6% and improves chip yield from 50% to... View More

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