IEEE - Institute of Electrical and Electronics Engineers, Inc. - Embedded DRAM for a reconfigurable array

1999 Symposium on VLSI Circuits. Digest of Technical Papers

Author(s): S. Perissakis ; Y. Joo ; J. Ahn ; A. Dellon ; J. Wawraynek
Sponsor(s): Japan Soc. Appl. Phys.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 17 June 1999
Page Count: 4
Page(s): 145 - 148
ISBN (Paper): 4-930813-95-6
DOI: 10.1109/VLSIC.1999.797266
Regular:

A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be... View More

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