IEEE - Institute of Electrical and Electronics Engineers, Inc. - A DRAM system for consistently reducing CPU wait cycles

1999 Symposium on VLSI Circuits. Digest of Technical Papers

Author(s): Y. Kanno ; H. Mizuno ; T. Watanabe
Sponsor(s): Japan Soc. Appl. Phys.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 17 June 1999
Page Count: 2
Page(s): 131 - 132
ISBN (Paper): 4-930813-95-6
DOI: 10.1109/VLSIC.1999.797261
Regular:

This paper describes a DRAM system for consistently reducing CPU wait cycles for an access to DRAMs in a cache-based memory hierarchy. An arithmetical address mapping circuitry and a pseudo... View More

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