IEEE - Institute of Electrical and Electronics Engineers, Inc. - 10-100 Gb/s throughput CMOS techniques

1999 Symposium on VLSI Circuits. Digest of Technical Papers

Author(s): C. Svensson ; A. Edman
Sponsor(s): Japan Soc. Appl. Phys.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 17 June 1999
Page Count: 4
Page(s): 65 - 68
ISBN (Paper): 4-930813-95-6
DOI: 10.1109/VLSIC.1999.797238
Regular:

Basic limitations to high data throughput chips in CMOS are described and methods for coping with these discussed. The proposed methods are demonstrated by two design examples;: a pipelined... View More

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