IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 50 Gb/s 32/spl times/32 CMOS crossbar chip using asymmetric serial links

1999 Symposium on VLSI Circuits. Digest of Technical Papers

Author(s): Kun-Yung Ken Chang ; Shang-Tse Chuang ; N. McKeown ; M. Horowitz
Sponsor(s): Japan Soc. Appl. Phys.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 17 June 1999
Page Count: 4
Page(s): 19 - 22
ISBN (Paper): 4-930813-95-6
DOI: 10.1109/VLSIC.1999.797221
Regular:

A 32/spl times/32 synchronous crossbar chip was designed in a 0.27 /spl mu/m CMOS technology for use in a high-speed network switch. The crossbar chip uses 32 Asymmetric Serial Links to achieve... View More

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