IEEE - Institute of Electrical and Electronics Engineers, Inc. - Haystack syndrome avoidance on massive correlation for probe vs. E-test data through the concurrent use of tree base models and trellis graphics. Application on sub-micron mix-signal product for the determination of the best process conditions for yield maximisation

1999 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings

Author(s): Ortega, C. ; Ignacio Alonso, J. ; Sobrino, E. ; Bonal, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Boston, Massachusetts, USA, USA
Conference Date: 8 September 1999
Page(s): 76 - 79
ISBN (Paper): 0-7803-5217-3
ISSN (Paper): 1078-8743
DOI: 10.1109/ASMC.1999.798185
Regular:

In an environment which requires an intensive capitalisation like the semiconductor industry, time-detection/time-reaction to any kind of yield degradation is a key issue. Abundant... View More

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