IEEE - Institute of Electrical and Electronics Engineers, Inc. - TAT- and cost-reduction strategies in LSI manufacturing test process

1999 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 99 Proceedings

Author(s): Fujioka, H. ; Nakamae, K. ; Chikamura, A. ; Kitamura, M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Boston, Massachusetts, USA, USA
Conference Date: 8 September 1999
Page(s): 59 - 63
ISBN (Paper): 0-7803-5217-3
ISSN (Paper): 1078-8743
DOI: 10.1109/ASMC.1999.798182
Regular:

Testing strategies in the test process composed of a wafer-probe testing phase, an LSI assembly and packaging phase, and a final testing phase are discussed to reduce the turn around time and... View More

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