IEEE - Institute of Electrical and Electronics Engineers, Inc. - Enabling shallow trench isolation for 0.1 /spl mu/m technologies and beyond

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): C.-P. Chang ; S.F. Shive ; S.C. Kuehne ; Y. Ma ; H. Vuong ; F.H. Baumann ; M. Bude ; E.J. Lloyd ; C.S. Pai ; M.A. Abdelgadir ; R. Dail ; C.T. Liu ; K.P. Cheung ; J.I. Colonell ; W.Y.C. Lai ; J.F. Miner ; H. Vaidya ; R.C. Liu ; J.T. Clemens
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 161 - 162
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799393
Regular:

Shallow trench isolation (STI) has become the standard isolation structure for sub-micron silicon CMOS technologies (Perera et al, 1995; Chatterjee et al, 1996). However, following the trend of... View More

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