IEEE - Institute of Electrical and Electronics Engineers, Inc. - New embedded DRAM technology using self-aligned salicide block (SSB) process for 0.18 /spl mu/m SOC (system on a chip)

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): K. Kokubun ; H. Takato ; T. Sakurai ; H. Koike ; A. Nomachi ; H. Ohtsuka ; H. Harakawa ; W. Sato ; M. Tanaka ; H. Naruse ; H. Kamijo ; J. Kumagai ; H. Ishiuchi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 155 - 156
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799390
Regular:

New embedded DRAM technology for 0.18 /spl mu/m SOC (system on a chip) using the self-aligned salicide block (SSB) process is proposed. This process technology provides full process compatibility... View More

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