IEEE - Institute of Electrical and Electronics Engineers, Inc. - Realization of 0.1 /spl mu/m buried-channel PMOSFETs by device restructuring using tilted well implantation technology

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): T. Tanaka ; Y. Momiyama ; K. Goto ; Y. Sambonsugi ; M. Deura ; T. Sugii
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 109 - 110
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799364
Regular:

Device restructuring by tilted well implantation (TWI) was proposed for highly cost effective system LSIs. We demonstrated a 0.1 /spl mu/m buried-channel (BC) PMOSFET with a superior I/sub... View More

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