IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 0.10-/spl mu/m CMOS device with a 40-nm gate sidewall and multilevel interconnects for system LSI

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): H. Wakabayashi ; T. Yamamoto ; Y. Saito ; T. Ogura ; M. Narihiro ; K. Tsuji ; T. Fukai ; K. Uejima ; Y. Nakahara ; K. Takeuchi ; Y. Ochiai ; T. Mogami ; T. Kunio
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 107 - 108
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799363
Regular:

A 0.10 /spl mu/m CMOS device for system LSI was successfully integrated with a 40 nm gate sidewall (SW) using a local-channel structure, an offset spacer, highly-doped source/drain extensions... View More

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