IEEE - Institute of Electrical and Electronics Engineers, Inc. - 0.1 /spl mu/m CMOS with shallow and steep source/drain extensions fabricated by using rapid vapor-phase doping (RVD)

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): T. Uchino ; Y. Kiyota ; T. Shiba
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 93 - 94
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799356
Regular:

We have developed an advanced 0.1 /spl mu/m CMOS technology to form 39 nm deep p-type junctions with sheet resistance as low as 630 /spl Omega//sq using two techniques in combination: rapid... View More

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