IEEE - Institute of Electrical and Electronics Engineers, Inc. - A self-aligned split-gate flash EEPROM cell with 3-D pillar structure

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): F. Hayashi ; J.D. Plummer
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 87 - 88
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799353
Regular:

A novel 3D memory cell has been proposed for high density future generation flash EEPROMs. A self-aligned split-gate (SASG) structure, minimizing the split-gate length, has been implemented in a... View More

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