IEEE - Institute of Electrical and Electronics Engineers, Inc. - Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): C.T. Liu ; F.H. Baumann ; A. Ghetti ; H.H. Vuong ; C.P. Chang ; K.P. Cheung ; J.I. Colonell ; W.Y.C. Lai ; E.J. Lloyd ; J.F. Miner ; C.S. Pai ; H. Vaidya ; R. Liu ; J.T. Clemens
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 75 - 76
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799347
Regular:

In the fabrication of CMOS devices with sub-3 nm gate oxides, we have observed severe variation of the oxide thickness (t/sub ox/). For devices with 2.5 nm t/sub ox/ at the center of the channel,... View More

Advertisement