IEEE - Institute of Electrical and Electronics Engineers, Inc. - An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 /spl mu/m CMOS low-voltage applications

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): Y.V. Ponomarev ; P.A. Stolk ; A.C.M.C. Van Brandenburg ; C.J.J. Dachs ; M. Kaiser ; A.H. Montree ; R. Roes ; J. Schmitz ; P.H. Woerlee
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 65 - 66
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799342
Regular:

We have studied an aggressive lateral MOS channel profiling combined with gate work function engineering for sub-0.13 /spl mu/m generation PMOSFETs oriented for low-voltage operation. In this... View More

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