IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low resistance Co-salicided 0.1 /spl mu/m CMOS technology using selective Si growth

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): S. Shimizu ; Y. Nishida ; T. Kuroi ; Y. Kanda ; M. Fujisawa ; Y. Inoue ; T. Nishimura ; T. Oishi ; T. Nakahata ; Y. Abe ; S. Maruno ; Y. Tokuda ; S. Satoh
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 55 - 56
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799337
Regular:

A low resistance salicided 0.1 /spl mu/m CMOSFET has been developed with precisely controlled T-shaped gate and optimum gate structure for thick CoSi/sub 2/. Selective Si growth (SSG) using a... View More

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