IEEE - Institute of Electrical and Electronics Engineers, Inc. - A source/drain formation technology utilizing sub-10 keV arsenic and assist-phosphorus implantation for 0.13 /spl mu/m MOSFET

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): K. Imai ; S. Shishiguchi ; K. Yamaguchi ; N. Kimizuka ; H. Onishi ; T. Horiuchi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 51 - 52
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799335
Regular:

We have developed a novel technology for formation of source/drain regions in 0.13 /spl mu/m MOSFETs. A combination of low-energy arsenic (8 keV) implantation and assist-phosphorous implantation... View More

Advertisement