IEEE - Institute of Electrical and Electronics Engineers, Inc. - Co salicide compatible 2-step activation annealing process for deca-nano scaled MOSFETs

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): K.-I. Goto ; Y. Sambonsugi ; T. Sugii
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 49 - 50
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799334
Regular:

Recently, to realize a high performance deca-nano scaled MOSFET, we reported a new MOSFET fabrication process named the "2-step activation annealing process" (2-step AAP) (Goto et al, 1997), which... View More

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