IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 0.9 V operation 2-transistor flash memory for embedded logic LSIs

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): K. Takahashi ; H. Doi ; N. Tamura ; K. Mimuro ; T. Hashizume ; Y. Moriyama ; Y. Okuda
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 21 - 22
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799320
Regular:

A novel 2-transistor flash memory cell is proposed to meet the read performance of mask ROMs. A very low 0.9 V nonword-line-boosting read operation is successfully achieved by employing a... View More

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