IEEE - Institute of Electrical and Electronics Engineers, Inc. - A low voltage erase technique for DINOR flash memory devices

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): Zhizheng Liu ; T.P. Ma
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 17 - 18
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799318
Regular:

A novel low voltage (/spl les/5 V) erase scheme for DINOR (divided bit line NOR) flash memory devices, designated pulse agitated substrate hot electron injection (PASHEI), is demonstrated. No... View More

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