IEEE - Institute of Electrical and Electronics Engineers, Inc. - High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme

1999 Symposium on VLSI Technology. Digest of Technical Papers

Author(s): K. Tsuji ; K. Takeuchi ; T. Mogami
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Kyoto, Japan, Japan
Conference Date: 14 June 1999
Page Count: 2
Page(s): 9 - 10
ISBN (Paper): 4-930813-93-X
DOI: 10.1109/VLSIT.1999.799314
Regular:

It is demonstrated that low temperature activation of the source/drain impurities, induced by the re-crystallization of an amorphous substrate layer, is effective for realization of scaled CMOS... View More

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