IEEE - Institute of Electrical and Electronics Engineers, Inc. - Interconnect performance modeling for 3D integrated circuits with multiple Si layers

Proceedings of the IEEE 1999 International Interconnect Technology Conference

Author(s): Souri, S.J. ; Saraswat, K.C.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Francisco, CA, USA, USA
Conference Date: 26 May 1999
Page(s): 24 - 26
ISBN (Paper): 0-7803-5174-6
DOI: 10.1109/IITC.1999.787067
Regular:

Long interconnect RC delay is increasing rapidly with chip size, limiting chip performance. 3D device integration in multiple layers of Si promises to increase transistor packing density and... View More

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