IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design validation of .18 /spl mu/m 1 GHz cache and register arrays

1999 IEEE International Workshop on Memory Technology, Design and Testing

Author(s): Malone, D.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Jose, CA, USA, USA
Conference Date: 9 August 1999
Page(s): 54 - 60
ISBN (Paper): 0-7695-0259-8
ISSN (Paper): 1087-4852
DOI: 10.1109/MTDT.1999.782684
Regular:

This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 /spl mu/m 7LM copper BEOL technology. Results and approaches for assuring product... View More

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