IEEE - Institute of Electrical and Electronics Engineers, Inc. - Exploring silicon process technology through RIT'S NPN BJT process

Proceedings of the Thirteenth Biennial University/Government/Industry Microelectronics Symposium

Author(s): Hirschman, K.D. ; Rack, P.D.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Minneapolis, MN, USA
Conference Date: 23 June 1999
Page(s): 94 - 98
ISBN (Paper): 0-7803-5240-8
ISSN (Paper): 0749-6877
DOI: 10.1109/UGIM.1999.782830
Regular:

At RIT, a vertical NPN BJT process laboratory is used in an intermediate level course in silicon process technology. The laboratory is designed to put into practice the theories (i.e. crystal... View More

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