IEEE - Institute of Electrical and Electronics Engineers, Inc. - Multiple-valued minimization to optimize PLAs with output EXOR gates

Proceedings of the 29th International Symposium on Multiple-Valued Logic

Author(s): Debnath, D. ; Sasao, T.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Freiburg, Germany, Germany
Conference Date: 20 May 1999
Page(s): 99 - 104
ISBN (Paper): 0-7695-0161-3
ISSN (Paper): 0195-623X
DOI: 10.1109/ISMVL.1999.779702
Regular:

This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP)... View More

Advertisement