IEEE - Institute of Electrical and Electronics Engineers, Inc. - Flip-flop selection technique for power-delay trade-off [video codec]

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition

Author(s): M. Hamada ; T. Terazawa ; T. Higashi ; S. Kitabayashi ; S. Mita ; Y. Watanabe ; M. Ashino ; H. Hara ; T. Kuroda
Sponsor(s): IEEE Solid State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Francisco, CA, USA
Conference Date: 17 February 1999
Page Count: 3
Page(s): 270 - 271
ISBN (Paper): 0-7803-5126-6
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.1999.759241
Regular:

Circuit and design techniques trade off power, delay, and area of a chip by blending different types of flip-flops with different merits: F/F blending. Three types of discrete cosine transform... View More

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