IEEE - Institute of Electrical and Electronics Engineers, Inc. - An 18 Mb, 12.3 GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition

Author(s): Cangsang Zhao ; U. Bhattacharya ; M. Denham ; J. Kolousek ; Yi Lu ; Yong-Gee Ng ; N. Nintunze ; K. Sarkez ; H. Varadarajan
Sponsor(s): IEEE Solid State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Francisco, CA, USA
Conference Date: 17 February 1999
Page Count: 3
Page(s): 200 - 201
ISBN (Paper): 0-7803-5126-6
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.1999.759193
Regular:

This 18 Mb pipeline-burst cache SRAM has 12.3 GB/s data transfer rate. The 14.3/spl times/14.6 mm/sup 2/ chip uses a 5.6 /spl mu/m/sup 2/ (2.22/spl times/2.52) 6-transistor cell and is fabricated... View More

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