IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 1.4 ns access 700 MHz 288 kb SRAM macro with expandable architecture

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition

Author(s): H. Shimizu ; K. Ijitsu ; H. Akiyoshi ; K. Aoyama ; H. Takatsuka ; K. Watanabe ; R. Nanjo ; Y. Takao
Sponsor(s): IEEE Solid State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Francisco, CA, USA
Conference Date: 17 February 1999
Page Count: 3
Page(s): 190 - 191
ISBN (Paper): 0-7803-5126-6
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.1999.759188
Regular:

This 1.4 ns 700 MHz 4 kword/spl times/72 b embedded SRAM macro is intended for applications such as cache memory for system LSIs. The macro employs an easily expandable architecture. An 8... View More

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