IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition

Author(s): K. Gotoh ; H. Tamura ; H. Takauchi ; Tsz Shing Cheung ; Weixin Gai ; Y. Koyanagi ; R. Schober ; R. Sastry ; F. Chen
Sponsor(s): IEEE Solid State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Francisco, CA, USA
Conference Date: 17 February 1999
Page Count: 3
Page(s): 180 - 181
ISBN (Paper): 0-7803-5126-6
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.1999.759182
Regular:

An I/O transceiver for scalable multiprocessor systems with 1.25 Gb/s parallel bandwidth and 7.7 ns latency performs as a plesiochronous link and compensates for skin-effect cable loss and... View More

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