IEEE - Institute of Electrical and Electronics Engineers, Inc. - A sub-40 ns random-access chain FRAM architecture with a 768 cell-plate-line drive

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition

Author(s): D. Takashima ; S. Shuto ; I. Kunishima ; H. Takenaka ; Y. Oowaki ; S. Tanaka
Sponsor(s): IEEE Solid State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Francisco, CA, USA
Conference Date: 17 February 1999
Page Count: 3
Page(s): 102 - 103
ISBN (Paper): 0-7803-5126-6
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.1999.759147
Regular:

This work demonstrates a prototype of nonvolatile chain ferroelectric RAM (chain FRAM), with fast compact cell-plate-line drive. A 16 kb chain FRAM test chip using 0.5 /spl mu/m 2-metal CMOS... View More

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