IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 500 MHz 64b RISC CPU with 1.5 MB on-chip cache

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition

Author(s): P. Barnes
Sponsor(s): IEEE Solid State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: San Francisco, CA, USA
Conference Date: 17 February 1999
Page Count: 2
Page(s): 86 - 87
ISBN (Paper): 0-7803-5126-6
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.1999.759129
Regular:

A 64b quad issue PA-RISC microprocessor with full out-of-order execution is migrated from 0.5 /spl mu/m CMOS into an advanced 0.25 /spl mu/m CMOS process. Features include an integrated on-chip... View More

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